IO memory space layout

The PCIIA cards use a very specific IO memory space allocation layout. The address bits A0 through A9 (which have traditionally been the only address bits evaluated on IBM PC XT extension cards) are hardwired to address 0x2e1. Bits A10 through A12 are used by the µPD7210 register select lines. This makes the individual 7210 registers being 0x400 bytes apart in the ISA bus address space. Address bits A13 and A14 are compared to a DIP switch setting on the card, allowing for up to 4 different cards being installed (at base addresses 0x2e1, 0x22e1, 0x42e1, and 0x62e1, respectively). A15 has been used to select an optional on-board time-of-day clock chip (MM58167A) on the original PCIIA rather than the µPD7210 (which is not implemented on later boards and clones). Finally, the IO addresses 0x2f0 ... 0x2f7 are used for a special interrupt handling feature (re-enable interrupts so the IRQ can be shared), where actually only address 0x2f0 plus the actual IRQ level is required for each card. Some clones do not appear to require this special IRQ handling, and are thus likely to not support the shared IRQ feature.

Only the base address of the card needs to be specified in the ISA device hints; the driver takes care to derive all other IO addresses needed during the probe phase.

Supported cards

The following cards are known to be supported:

• B&C Microsystems PC488A-0
• National Instruments GPIB-PCII/PCIIA (in PCIIa mode)
• Axiom AX5488