DESCRIPTION
Intel Sandy Bridge CPUs contain PMCs conforming to version 3 of the Intel performance measurement architecture. These CPUs contain two classes of PMCs:
-
PMC_CLASS_UCF
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Fixed-function counters that count only one hardware event per counter.
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PMC_CLASS_UCP
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Programmable counters that may be configured to count one of a defined set of hardware events.
The number of PMCs available in each class and their widths need to be determined at run time by calling pmc_cpuinfo(3).
Intel Sandy Bridge PMCs are documented in Volume 3B: System Programming Guide, Part 2, Intel(R) 64 and IA-32 Architectures Software Developers Manual, Order Number: 253669-039US, Intel Corporation, May 2011.
SANDYBRIDGE UNCORE FIXED FUNCTION PMCS
These PMCs and their supported events are documented in
pmc.ucf(3). Not all CPUs in this family implement fixed-function counters.
SANDYBRIDGE UNCORE PROGRAMMABLE PMCS
The programmable PMCs support the following capabilities:
| Capability |
Support |
| PMC_CAP_CASCADE |
No |
| PMC_CAP_EDGE |
Yes |
| PMC_CAP_INTERRUPT |
No |
| PMC_CAP_INVERT |
Yes |
| PMC_CAP_READ |
Yes |
| PMC_CAP_PRECISE |
No |
| PMC_CAP_SYSTEM |
No |
| PMC_CAP_TAGGING |
No |
| PMC_CAP_THRESHOLD |
Yes |
| PMC_CAP_USER |
No |
| PMC_CAP_WRITE |
Yes |
Event Qualifiers
Event specifiers for these PMCs support the following common qualifiers:
-
cmask=
value
-
Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to
value.
-
edge
-
Configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true.
-
inv
-
Invert the sense of comparison when the “
cmask” qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the “
cmask” qualifier.
Event Specifiers (Programmable PMCs)
Sandy Bridge programmable PMCs support the following events:
-
CBO_XSNP_RESPONSE.RSPIHITI
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(Event 22H, Umask 01H) Snoop responses received from processor cores to requests initiated by this Cbox. Must combine with one of the umask values of 20H, 40H, 80H
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CBO_XSNP_RESPONSE.RSPIHITFSE
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(Event 22H, Umask 02H) Must combine with one of the umask values of 20H, 40H, 80H
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CBO_XSNP_RESPONSE.RSPSHITFSE
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(Event 22H, Umask 04H) Must combine with one of the umask values of 20H, 40H, 80H
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CBO_XSNP_RESPONSE.RSPSFWDM
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(Event 22H, Umask 08H)
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CBO_XSNP_RESPONSE.RSPIFWDM
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(Event 22H, Umask 01H)
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CBO_XSNP_RESPONSE.AND_EXTERNAL
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(Event 22H, Umask 20H) Filter on cross-core snoops resulted in external snoop request. Must combine with at least one of 01H, 02H, 04H, 08H, 10H
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CBO_XSNP_RESPONSE.AND_XCORE
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(Event 22H, Umask 40H) Filter on cross-core snoops resulted in core request. Must combine with at least one of 01H, 02H, 04H, 08H, 10H
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CBO_XSNP_RESPONSE.AND_XCORE
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(Event 22H, Umask 80H) Filter on cross-core snoops resulted in LLC evictions. Must combine with at least one of 01H, 02H, 04H, 08H, 10H
-
CBO_CACHE_LOOKUP.M
-
(Event 34H, Umask 01H) LLC lookup request that access cache and found line in M-state. Must combine with one of the umask values of 10H, 20H, 40H, 80H
-
CBO_CACHE_LOOKUP.E
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(Event 34H, Umask 02H) LLC lookup request that access cache and found line in E-state. Must combine with one of the umask values of 10H, 20H, 40H, 80H
-
CBO_CACHE_LOOKUP.S
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(Event 34H, Umask 04H) LLC lookup request that access cache and found line in S-state. Must combine with one of the umask values of 10H, 20H, 40H, 80H
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CBO_CACHE_LOOKUP.I
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(Event 34H, Umask 08H) LLC lookup request that access cache and found line in I-state. Must combine with one of the umask values of 10H, 20H, 40H, 80H
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CBO_CACHE_LOOKUP.AND_READ
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(Event 34H, Umask 10H) Filter on processor core initiated cacheable read requests. Must combine with at least one of 01H, 02H, 04H, 08H
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CBO_CACHE_LOOKUP_AND_READ2
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(Event 34H, Umask 20H) Filter on processor core initiated cacheable write requests. Must combine with at least one of 01H, 02H, 04H, 08H
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CBO_CACHE_LOOKUP.AND_EXTSNP
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(Event 34H, Umask 40H) Filter on external snoop requests. Must combine with at least one of 01H, 02H, 04H, 08H
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CBO_CACHE_LOOKUP.AND_ANY
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(Event 34H, Umask 80H) Filter on any IRQ or IPQ initiated requests including uncacheable, noncoherent requests. Must combine with at least one of 01H, 02H, 04H, 08H
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IMPH_CBO_TRK_OCCUPANCY.ALL
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(Event 80H, Umask 01H) Counts cycles weighted by the number of core-outgoing valid entries. Valid entries are between allocation to the first of IDIO or DRSO messages. Accounts for coherent and incoherent traffic. Counter 0 only
-
IMPH_CBO_TRK_REQUEST.ALL
-
(Event 81H, Umask 01H) Counts the number of core-outgoing entries. Accounts for coherent and incoherent traffic.
-
IMPH_CBO_TRK_REQUEST.WRITES
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(Event 81H, Umask 20H) Counts the number of allocated write entries, include full, partial, and evictions.
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IMPH_CBO_TRK_REQUEST.EVICTIONS
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(Event 81H, Umask 80H) Counts the number of evictions allocated.
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IMPH_COH_TRK_OCCUPANCY.ALL
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(Event 83H, Umask 01H) Counts cycles weighted by the number of core-outgoing valid entries in the coherent tracker queue. Counter 0 only
-
IMPH_COH_TRK_REQUEST.ALL
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(Event 84H, Umask 01H) Counts the number of core-outgoing entries in the coherent tracker queue.